The blocks are a way to read a link. They do not all have to appear in the same assembly. Every rate, loss, and distance on this page stays inside the wording of the OIF document it cites.
Choose a pathSource
Laser inside the engine
External continuous wave
VCSEL
ModulatorExternal CW light passes through it
DetectorForm is not uniform
Choose an electrical styleDrive / receive
Retimed
Linear
Half-retimed
Direct drive
ExitPigtail or connector
Left to right is a reading order. Dashed boxes are alternate paths, not required parts.
筹备中 · In preparation规划方向 · Planned scope
Modulation and detection
Where a silicon photonic engine keeps the laser outside, the framework describes continuous-wave light entering modulators and leaving as a modulated stream. In an OIF ECOC 2024 deck, a 3.2T co-packaged module example draws the optical side as laser, modulator, and photodetector, and the electrical IC as driver, TIA, and control.
What changes between designs That drawing is a functional split inside a co-packaged module example, not an NPO bill of materials. The framework’s four electrical styles — direct drive, linear amplified, half-retimed, and retimed — leave different amounts of clock recovery and gain inside the engine. Germanium photodetectors appear in the ELSFP thermal comparison; that does not make every receiver germanium.
At device level the public paths are an in-engine laser, an external continuous-wave laser, and the VCSEL the framework discusses for short reach. Multiple wavelengths and a single wavelength correspond to different optical examples, including the 400GBASE-FR4 and DR4 links the framework names, and the short-reach SR4 and VR4 links.
What changes between designs Those IEEE 802.3 names are application examples in the framework, for engines meant to interoperate with installed cabling. They are not NPOTEC module codes. One laser may feed a single lane, or be split and combined on the source side or the engine side. The management white paper also says the implementer decides how many engines one source module feeds.
When OIF started CEI-112G-XSR in 2018, the target was intra-package die-to-die and die-to-optical-engine links, 72–116 Gbps, a reach target up to 50 mm, and explicitly a CMOS-to-SiGe mix, because SiGe is frequently used to build optical engines. The 2024 summary of the published CEI-112G-XSR+-PAM4 agreement states 112 Gb/s PAM4, bump-to-bump insertion loss up to 13 dB at Nyquist, 36–58 Gsym/s, intended for multichip modules, co-packaged optics, and near-package optics.
What changes between designs The 50 mm figure is how the XSR project, and the framework’s retimed example, talk about distance. The framework also says the achievable distance depends on loss, crosstalk, parasitics, and impedance discontinuities, and that on some Figure 2 use-cases XSR may be insufficient and an enhanced interface may be required. XSR+ covers three assembly classes. It is not NPO-only, and it is not the electrical interface of every near-package build. Pluggable modules sit on a different chip-to-module class: the CEI-112 fact sheet defines the Very Short Reach project as chip-to-module.
The framework splits the data fiber’s exit into a pigtail or a connector. If the external source is an ELSFP, continuous-wave light uses a blind-mate optical connection on a faceplate module to enter the system. The implementation agreement requires IEC 60825-2 Hazard Level 1 when the module is used as specified.
What changes between designs The continuous-wave inlet and the data-fiber outlet are two interfaces. The management white paper’s example says a 3.2 Tb/s optical engine has either 4 or 8 CW inputs, and an ELSFP has up to 16 CW outputs; the system vendor chooses the pairing. Those numbers are examples in that paper, not an NPO port quota.